1. Field of the Invention
The embodiments discussed herein are related to a semiconductor device and manufacturing method of the semiconductor device.
2. Description of the Related Art
Conventionally, a semiconductor device of a superjunction (SJ) structure (hereinafter, superjunction semiconductor device) is known that has a drift layer made as a parallel pn layer with an n-type region and a p-type region of increased impurity concentration alternately arranged in a direction parallel to a chip principal surface (horizontal direction). In the superjunction semiconductor device, in the on-state, current flows to the n-type region of the parallel pn layer and in the off-state, a depletion layer extends also from a pn junction between the n-type region and the p-type region of the parallel pn layer and the n-type region and the p-type region are depleted and bear a breakdown voltage. In the superjunction semiconductor device, since the impurity concentration of the drift layer can be increased, on-state resistance can be decreased while maintaining a high breakdown voltage.
With respect to such a superjunction semiconductor device, a device is proposed that has the parallel pn layer with the n-type region and the p-type region arranged in a planar layout of a stripe having a same width and extending from an element active portion to a high voltage structure (for example, refer to Japanese Laid-Open Patent Publication No. 2008-294214 (paragraph 0020, FIGS. 1 and 2)). In Japanese Laid-Open Patent Publication No. 2008-294214, the breakdown voltage of the high voltage structure is made higher than that of the element active portion by making the impurity concentration of the parallel pn layer in the high voltage structure lower than that of the parallel pn layer in the element active portion. The element active portion is a region in which current flows in the on-state. An element edge portion surrounds the element active portion. The high voltage structure is arranged in the element edge portion and is a region that relaxes electric field on the top surface side of the chip and holds the breakdown voltage.
As another superjunction semiconductor device, a device is proposed in which a repetitive pitch of the n-type region and the p-type region of the parallel pn layer is made narrower in the high voltage structure than in the element active portion (for example, refer to Japanese Laid-Open Patent Publication No. 2002-280555 (paragraph 0023, FIG. 6) and International Publication No. 2013/008543 (paragraph 0032, FIGS. 1 and 2)). In Japanese Laid-Open Patent Publication No. 2002-280555, the parallel pn layer having the n-type region and the p-type region arranged in the stripe-like planar layout is disposed in both the element active portion and the high voltage structure. In International Publication No. 2013/008543, the parallel pn layer having the n-type region and the p-type region arranged in the stripe-like planar layout is disposed in the element active portion and the parallel pn layer having the p-type region arranged in a matrix-like planar layout inside the n-type region is disposed in the high voltage structure.
As another superjunction semiconductor device, a device is proposed in which the n-type region and the p-type region of the parallel pn layer are arranged in the stripe-like planar layout and a width in a lateral direction orthogonal to the stripe (hereinafter referred to simply as width) of the n-type region and the p-type region of the parallel pn layer in the high voltage structure is partially changed (for example, refer to Japanese Laid-Open Patent Publication No. 2010-056154). As another superjunction semiconductor device, a device is proposed in which the n-type region and the p-type region of the parallel pn layer are arranged in the stripe-like planar layout and in the vicinity of the boundary with the high voltage structure, the width of the p-type region of the parallel pn layer in the element active portion is gradually narrowed outwardly (for example, refer to Japanese Laid-Open Patent Publication No. 2012-160752 (paragraph 0051, FIGS. 18 and 19)).
In Japanese Laid-Open Patent Publication No. 2002-280555, International Publication No. 2013/008543, and Japanese Laid-Open Patent Publication Nos. 2010-056154 and 2012-160752, by changing the repetitive pitch of the n-type region and the p-type region of the parallel pn layer or the width of the p-type region of the parallel pn layer, between the element active portion and the high voltage structure, the impurity concentration of the parallel pn layer in the high voltage structure is made lower than that of the parallel pn layer in the element active portion. For this reason, in the same manner as in Japanese Laid-Open Patent Publication No. 2008-294214, the breakdown voltage of the high voltage structure is made higher than that of the element active portion.
As to a parallel pn layer forming method, a method is proposed of ion-implanting the n-type impurity over the entire surface, selectively ion-implanting the p-type impurity using a resist mask, and then diffusing the impurity by heat treatment, each time a non-doped layer is stacked on another by the epitaxial growth (for example, refer to Japanese Laid-Open Patent Publication No. 2011-192824 (paragraph 0025, FIGS. 1 to 4)). In Japanese Laid-Open Patent Publication No. 2011-192824, with consideration of a subsequent thermal diffusion process, the opening width of the resist mask used for the p-type impurity ion-implantation is set on the order of ¼ of the remaining width and accordingly, the implanting quantity of the p-type impurity is set on the order of 4 times the implanting quantity of the n-type impurity, thereby making the total impurity quantities of the n-type region and the p-type region of the parallel pn layer equal.
As to another parallel pn layer forming method, a method is proposed of selectively ion-implanting the n-type impurity and the p-type impurity, using different resist masks, and then diffusing the impurity by the heat treatment, each time an n-type high resistance layer is stacked upon another by the epitaxial growth (for example, refer to Japanese Laid-Open Patent Publication No. 2000-040822 (paragraph Nos. 0032 to 0035, FIG. 4)). In Japanese Laid-Open Patent Publication No. 2000-040822, the n-type impurity implanting region that becomes the n-type region of the parallel pn layer and the p-type impurity implanting region that becomes the p-type region of the parallel pn layer are selectively formed so as to oppose each other in the lateral direction and be thermally diffused. This makes it possible to cause both the n-type region and the p-type region to have high impurity concentration and suppress variation in the impurity concentration in the vicinity of the pn junction with the laterally adjacent region.
As a result of an intensive research by inventors, however, it has been found out that in the case of forming the parallel pn layer in the element active portion and the high voltage structure by selectively ion-implanting the n-type impurity and the p-type impurity as in Japanese Laid-Open Patent Publication No. 2000-040822, there arises the following problem. FIGS. 27A, 27B, 28A, and 28B are top views of the planar layout of the parallel pn layer of a conventional superjunction semiconductor device. FIGS. 27A and 28A depict the planar layout at the time of completion of the parallel pn layer. FIGS. 27A and 28A depict a quarter of the conventional superjunction semiconductor device. FIGS. 27B and 28B depict the state during formation of the parallel pn layer in a boundary region 100b between an element active portion 100a and a high voltage structure 100c. An element edge portion 100d is formed by the boundary region 100b and the high voltage structure 100c. In FIGS. 27A, 27B, 28A, and 28B, the lateral direction in which the stripe of the parallel pn layer extends is given as y and the lateral direction orthogonal to the stripe is given as x. Reference numeral 101 denotes an n− type semiconductor layer to be epitaxially grown for the formation of the parallel pn layer.
As depicted in FIGS. 27A and 28A, in the conventional superjunction semiconductor device, a parallel pn layer (hereinafter, first parallel pn layer) 104 of the element active portion 100a and a parallel pn layer (hereinafter, second parallel pn layer) 114 of the high voltage structure 100c both extend to the boundary region 100b between the element active portion 100a and the high voltage structure 100c and contact each other. As depicted in FIGS. 27B and 28B, at the time of formation of the first and the second parallel pn layers 104 and 114, an n-type impurity implanting region 121 that becomes a first n-type region 102 of the first parallel pn layer 104 and a p-type impurity implanting region 122 that becomes a first p-type region 103 are each formed so as to extend to a first region 100e on the inner side (on the element active portion 100a side) of the boundary region 100b. N-type impurity implanting regions 131 and 141 that become second n-type regions 112 and 115 of the second parallel pn layer 114 and p-type impurity implanting regions 132 and 142 that become second p-type regions 113 and 116 are each formed so as to extend to a second region 100f on the outer side (on the high voltage structure 100c side) of the boundary region 100b. Each of these impurity implanting regions extends to the boundary (vertical dotted lines) of the first region 100e and the second region 100f. 
As depicted in FIGS. 27B and 28B, when the repetitive pitch P11 of the first n-type region 102 and the first p-type region 103 and the repetitive pitch P12 of the second n-type region 112 and the second p-type region 113 are made equivalent (P11=P12), the same conductive type regions of the first and the second parallel pn layers 104 and 114 are all in the state of contacting each other. Namely, the n-type impurity implanting regions 121 and 131 that become the first and the second n-type regions 102 and 112, and the p-type impurity implanting regions 122 and 132 that become the first and the second p-type regions 103 and 113, are respectively arranged in the planar layout of stripe continuing from the element active portion 100a to the high voltage structure 100c. For this reason, while the charge balance of the first and the second parallel pn layers 104 and 114 is not broken at the boundary region 100b, no breakdown voltage difference is caused between the element active portion and the high voltage structure since the first and the second parallel pn layers 104 and 114 have the same average impurity concentration. Therefore, a problem arises in that the electric field easily concentrates locally on the high voltage structure 100c whereby the breakdown voltage of the entire element is determined by the breakdown voltage of the high voltage structure 100c. 
On the other hand, as depicted in FIGS. 28A and 28B, when the repetitive pitch P12 of the second n-type region 115 and the second p-type region 116 is made narrower than the repetitive pitch P11 of the first n-type region 102 and the first p-type region 103 (P11>P12), the cycle at which the same conductive type regions of the first and the second parallel pn layers 104 and 114 contact each other is determined on the basis of the ratio of the repetitive pitches P11 and P12. Namely, in the boundary region 100b, with respect to the n-type impurity implanting regions 121 and 141 that become the first and the second n-type regions 102 and 115, and the p-type impurity implanting regions 122 and 142 that become the first and the second p-type regions 103 and 116, the same type impurity implanting regions contact each other at some locations and do not contact each other at other locations. For this reason, in the boundary region 100b, the n-type impurity concentration and the p-type impurity concentration are increased. For example, around a location 143 where the p-type impurity implanting regions 122 and 142 contact each other and become continuous, since the distances to adjacent n-type impurity implanting regions 121 and 141 differ, the p-type impurity concentration is higher than the n-type impurity concentration. Therefore, it is difficult to secure the charge balance at the boundary between the first parallel pn layer 104 and the second parallel pn layer 114 and a problem arises in that the breakdown voltage of the boundary region 100b decreases partially. With respect to this problem, although the partial decreasing of the breakdown voltage can be suppressed by making the average impurity concentration of the first and the second parallel pn layers 104 and 114 relatively low, the breakdown voltage of the entire element decreases.